1. Field of the Invention
The invention relates to methods of fabricating an integrated circuit, and more particularly to a method of reducing the fringe capacitance between a gate and a substrate.
2. Description of the Related Art
The dimension of semiconductor integrated circuits is being made smaller and smaller. During fabrication, every parameter is required to be accurate and precise since even a very tiny deviation may cause a fatal failure.
In FIG. 1, one conventional method of making a semiconductor device is presented. A semiconductor device including a substrate 100, a source 102 /drain 104, a poly-gate 106, a gate oxide 108 between the gate 106 and the substrate 100, and a pair of spacers 110 on the side wall of the gate 106 are shown in the figure. In addition, due to the hot electrons caused by a short channel, a pair of lightly doped regions are form between the source 102 and drain 104 under the gate 106.
If the thickness of the gate 106 is noted as H.sub.int, the thickness of the gate oxide 108 is t.sub.ox, there exists a gate fringe capacitance near the edge of the gate. The fringe capacitance C can be written as: ##EQU1## Thus, provided that all geometric parameters, such as H.sub.int and t.sub.ox, are kept in the same condition, the fringe capacitance C is proportional to the dielectric constant .epsilon. of the medium. In this case, the medium are the spacers 110. In conventional semiconductor devices, the material of the spacers is normally silicon oxide or silicon nitride. The dielectric constants of these two materials are about 3.9 and 7.5, respectively. It is known that the delay time .tau. is equal to the product of resistance R and the capacitance C. That is, .tau.=RC. Therefore, the very high dielectric constant of silicon oxide or silicon nitride causes a measurable fringe capacitance. Thus, a very long delay time which deteriorates the operation of device, or even the whole integrated circuit, occurs.